The present invention relates to a semiconductor memory device, and more particularly, an apparatus and method for testing a semiconductor memory device after finishing fabrication of the semiconductor memory device in a mass-production process.
A semiconductor memory device is used in a system as a data storage. When a data processing unit such as a central processing unit (CPU) requests data stored at a predetermined address, the semiconductor memory device provides the data to the central processing unit using address information received from the data processing unit. When the data processing unit sends data to the semiconductor memory device, the semiconductor memory device stores the data at an address specified by the data processing unit.
With the development of high-speed semiconductor systems and highly advanced semiconductor integrated circuits, semiconductor memory devices have been required to output and store data at higher speed. Furthermore, recent semiconductor memory devices are required to store more data, enable high-speed read/write operations, and consume less power. For these reasons, the design and manufacturing process for semiconductor memory devices have become more complicated, and thus the test procedures for finished semiconductor memory devices have become more complicated and difficult.
Due to the development of improved semiconductor manufacturing technology, a ratio of test cost for a finished semiconductor memory device to manufacturing process cost for the semiconductor memory device has been increased. In addition, semiconductor memory devices are manufactured using a much larger wafer, and more chips can be obtained from one wafer owing to the improvement in semiconductor manufacturing technology. As a result, it takes much more time to inspect finished semiconductor memory devices before packaging each chip of the semiconductor memory devices.
A plurality of chips of a wafer is simultaneously (not sequentially) inspected using a test apparatus. To this end, the test apparatus includes a probe card having a plurality of pins so that signals such as a test signal and a power signal can be simultaneously applied to a plurality of chips through the pins. The number of pins of the test apparatus cannot be increased above a predetermined level due to physical and cost-related limitations, thereby making it difficult to test semiconductor apparatuses more efficiently. However, since there is an increasing need for high-speed and high-capacity semiconductor memory devices, the number of pins of a probe card should be increased for rapidly testing each chip of a semiconductor memory device.
FIG. 1 is a block diagram explaining how a conventional semiconductor memory device is tested.
As shown, a chip 200 of the semiconductor memory device includes a signal input pad set 220 and an internal circuit 240. The signal input pad set 220 includes a plurality of signal input pads 221_1 to 222_I and a reference voltage pad 224 that are connected to an external test device 100 for testing the chip 200. The internal circuit 240 includes a plurality of input buffers 242_1 to 242_I for transmitting input signals inputted through the signal input set 220 from the external test device 100.
Each of the input buffers 242_1 to 242_I detects a corresponding input signal by comparing the input signal with a reference voltage VREF received through the reference voltage pad 224. Hence, the semiconductor memory device with the chip 200 can be normally operated at a low power voltage, and the power consumption of a system including the semiconductor memory device can be reduced. Specifically, when the semiconductor memory device is operated at a low power voltage, the swing width of control signals or data signals to/from the semiconductor memory device can be lowered. In this case, it is difficult for an input/output circuit to detect a data or control signal. Therefore, the input buffers 242_1 to 242_I are designed to detect the input signals by comparing the input signals with the reference voltage VREF received through the reference voltage pad 224.
In this case, since the reference voltage VREF as well as the input signals has to be applied to each chip 200 of the semiconductor memory device for testing the semiconductor memory device, the external test device 100 should have many probe card pins for simultaneously testing a plurality of chips of the semiconductor memory device. That is, the number of probe card pins of the external test device 100 has to be increased in proportion to the number of chips that are to be simultaneously tested, thereby making it difficult to make a probe card of the external test device 100. As a result, test costs increase.